The present invention relates to a semiconductor device in which a plurality of wells of one conductivity type are provided in a semiconductor body of the opposite conductivity type.
P- and N-channel transistors are formed in a single semiconductor substrate to constitute an IC semiconductor device having, for example, CMOS circuits. In this case, if an N-channel transistor is formed in a surface area of, for example, a P-type silicon substrate, N-type wells for P-channel transistors must be formed in the surface area of the substrate.
FIG. 1 shows one of the CMOS circuits in an IC semiconductor device. An N-type well 12 is formed in a surface area of a P-type substrate 14 as described above. N.sup.+ -type regions 16 and 18 serving as a source and a drain of an N-channel transistor, respectively, and a P.sup.+ -type region 20 for setting the potential of the substrate 14 are formed in the surface area thereof. P.sup.+ -type regions 22 and 24 serving as a source and a drain of a P-channel transistor, respectively, are formed in a surface area of the N-type well 12. An N.sup.+ -type region 26 for setting the potential of the N-type well 12 is formed in its surface area. Then, the surface area of the substrate 14 including the well 12 is covered by an insulation layer 28, and a gate electrode 30 of the N-channel transistor is formed on that portion of the substrate 14 which lies between the regions 16 and 18. Subsequently, a gate electrode 32 of the P-channel transistor is formed on that portion of the well 12 which lies between the regions 22 and 24. An insulation layer 34 is formed on the insulation layer 28 to cover the gate electrodes 30 and 32. Electrodes 35 to 40 are respectively formed on the regions 20, 18, 16, 22, 24 and 26 through respective contact holes in the insulation layers 28 and 34, and are interconnected on the insulation layer 34 by a conductive pattern connected to another circuit (not shown). In such a structure, when a plurality of wells for P-channel transistors are formed in the substrate, electrodes for setting the potentials of these wells prevent the higher integration of the semiconductor elements, and a wiring pattern for interconnecting electrodes on the substrate becomes complex.
On the other hand, a P-channel transistor can be formed to have a structure shown in FIG. 2. In FIG. 2, an N.sup.+ -type region 26 is formed to be adjacent to a P.sup.+ -type region 24, and an electrode 44 is formed on the regions 24 and 26 in place of the electrodes 39 and 40 of FIG. 1. The same reference numerals as in FIG. 1 denote the same parts in FIG. 2. When P-channel transistors are formed in this manner, the number of electrodes can be reduced and higher integration can be achieved.
However, the potential of the electrode 44 must be maintained at a predetermined level. If the potential of the electrode 44 is changed to control characteristics such as a threshold voltage of a P-channel transistor in a CMOS circuit as shown in FIG. 2, the potential of the region 24 is also changed.